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authorGayatri Kammela <[email protected]>2020-10-06 15:47:01 -0700
committerHans de Goede <[email protected]>2020-10-07 23:06:24 +0200
commit652036bd5be0ac94fd1db851d72ece8ee133c74d (patch)
tree11be24d675904353122b756fa526909973ec4962 /tools/perf/scripts/python/export-to-sqlite.py
parente973f1d372dca5ac1d107ec6134f72e566fdf968 (diff)
platform/x86: intel_pmc_core: Fix TigerLake power gating status map
TigerLake's LPM power gating status register has errors in the bit-to-name mapping as well as with the marked reserved bits according to the actual implementation. Hence, update the right bit-to-name mapping and the reserved bits in accordance with actual implementation. Cc: Srinivas Pandruvada <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: David E. Box <[email protected]> Signed-off-by: Gayatri Kammela <[email protected]> Signed-off-by: David E. Box <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hans de Goede <[email protected]>
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