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| author | 谢致邦 (XIE Zhibang) <[email protected]> | 2017-01-04 21:30:58 +0800 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2018-07-30 18:59:01 -0700 |
| commit | 60bc84e227d24fdb1ac2211c574a88ecd7c836a0 (patch) | |
| tree | 22a4bace0305a2901f87130100cbe923ee484b37 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 968dc5a0eaca707f8eb2fbad57d9fbbf3284541e (diff) | |
MIPS: Loongson: Merge load addresses
Systems based upon the Loongson 1B & 1C CPUs share the same load
address, as do those based upon Loongson 1A. Unify the definition of
this load address to reduce duplication & avoid the need for an extra
Loongson 1A case in future.
[[email protected]: Rewrite commit message.]
Signed-off-by: 谢致邦 (XIE Zhibang) <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/14927/
Cc: [email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions