diff options
| author | Miquel Raynal <[email protected]> | 2020-09-11 19:31:38 +0200 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2020-09-21 22:08:34 +0100 |
| commit | 5b4458ebb4c8007dae7eaeb88cb52b2bb4879894 (patch) | |
| tree | 7fbcf3b8d0c6d5843d39f66b4a39d3d42d67db30 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 501ef013390b774e8e61000a78d1d640d6c3411d (diff) | |
ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization
As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.
The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions