x86/tsc: Drastically reduce the number of firmware bug warnings

Prior to the TSC ADJUST MSR being available, the method to set TSC's in
sync with each other naturally caused a small skew between cpu threads.
This was NOT a firmware bug at the time so introducing a whole avalanche
of alarming warning messages might cause unnecessary concern and customer
complaints. (Example: >3000 msgs in a 32 socket Skylake system.)

Simply report the warning condition, if possible do the necessary fixes,
and move on.

Signed-off-by: Mike Travis <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Dimitri Sivanich <[email protected]>
Reviewed-by: Russ Anderson <[email protected]>
Reviewed-by: Peter Zijlstra <[email protected]>
Cc: Prarit Bhargava <[email protected]>
Cc: Andrew Banman <[email protected]>
Cc: Bin Gao <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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