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| author | Pali Rohár <[email protected]> | 2021-11-24 16:59:44 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2021-12-06 14:12:57 +0000 |
| commit | 3be9d243b21724d49b65043d4520d688b6040b36 (patch) | |
| tree | 5e6ec412719ccdeae300102ab48ff1cf34845383 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 1f1050c5e1fefb34ac90a506b43e9da803b5f8f7 (diff) | |
PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
Since all PCI Express device Functions are required to implement the PCI
Express Capability structure, Capabilities List bit in PCI Status Register
must be hardwired to 1b. Capabilities Pointer register (which is already
set by pci-bride-emul.c driver) is valid only when Capabilities List is set
to 1b.
Link: https://lore.kernel.org/r/[email protected]
Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: [email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions