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authorGeert Uytterhoeven <[email protected]>2020-03-06 09:50:38 +0100
committerMark Brown <[email protected]>2020-03-13 17:06:34 +0000
commit30b435d54b84fd1f9c53a237dec3c224ec1e59c7 (patch)
tree53631431730f783cfa3021fc761a712d853d57b9 /tools/perf/scripts/python/export-to-sqlite.py
parenta079ff858cc0831f5bbad205016bfd88bf992bb1 (diff)
spi: dt-bindings: spi-controller: Fix spi-[rt]x-bus-width for slave mode
The descriptions for the spi-rx-bus-width and spi-tx-bus-width properties refer to "MISO" and "MOSI", which are not explained in the document. While these abbreviations are fairly common when talking about SPI, and thus may not need an explanation, they are not entirely correct in this context, as the SPI controller may be used in slave mode instead of master mode. Fix this by replacing them by "read transfers" resp. "write transfers", like is done for the spi-rx-delay-us and spi-tx-delay-us properties. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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