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author | José Roberto de Souza <[email protected]> | 2020-04-14 16:04:40 -0700 |
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committer | Rodrigo Vivi <[email protected]> | 2020-04-20 10:12:46 -0700 |
commit | 12399028751b887bdc2515f1a1e2c81b4fd74085 (patch) | |
tree | 03c7794a8ebed95f0957e035c0f0fd5169a5d710 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 335f62e7606a7921775d7cc73f0ad8ffd899bc22 (diff) |
drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
Right now dp.regs.dp_tp_ctl/status are only set during the encoder
pre_enable() hook, what is causing all reads and writes to those
registers to go to offset 0x0 before pre_enable() is executed.
So if i915 takes the BIOS state and don't do a modeset any following
link retraing will fail.
In the case that i915 needs to do a modeset, the DDI disable sequence
will write to a wrong register not disabling DP 'Transport Enable' in
DP_TP_CTL, making a HDMI modeset in the same port/transcoder to
not light up the monitor.
So here for GENs older than 12, that have those registers fixed at
port offset range it is loading at encoder/port init while for GEN12
it will keep setting it at encoder pre_enable() and during HW state
readout.
Fixes: 4444df6e205b ("drm/i915/tgl: move DP_TP_* to transcoder")
Cc: Matt Roper <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Signed-off-by: José Roberto de Souza <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit edcb9028d66b44d74ba4f8b9daa379b004dc1f85)
Signed-off-by: Rodrigo Vivi <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions