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| author | Ville Syrjälä <[email protected]> | 2021-03-10 21:43:51 +0200 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2021-03-11 21:36:55 +0200 |
| commit | 086877a12f36f7fffaaeb3b7842cf409093e13b8 (patch) | |
| tree | 6ee1a25cb0c4396de277488e5c940d928be99ac2 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 35bb28ece90dfb7f72b77ba529f25f79323d9581 (diff) | |
drm/i915: Tolerate bogus DPLL selection
Let's check that we actually found the PLL before doing the
port_clock readout, just in case the hardware was severly
misprogrammed by the previous guy. Not sure the hw would
even survive such misprogramming without hanging but no
real harm in checking anyway.
Cc: Karthik B S <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Karthik B S <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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