diff options
| author | Marc Zyngier <[email protected]> | 2021-10-17 13:42:17 +0100 |
|---|---|---|
| committer | Daniel Lezcano <[email protected]> | 2021-10-17 21:47:31 +0200 |
| commit | 012f188504528b8cb32f441ac3bd9ea2eba39c9e (patch) | |
| tree | 9e0ae47a3a10cc2af6f5c666965d8f4019565ebb /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 30aa08da35e07a51a81d489517a3f6fb5164b09c (diff) | |
clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations
The Applied Micro XGene-1 SoC has a busted implementation of the
CVAL register: it looks like it is based on TVAL instead of the
other way around. The net effect of this implementation blunder
is that the maximum deadline you can program in the timer is
32bit wide.
Use a MIDR check to notice the broken CPU, and reduce the width
of the timer to 32bit.
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Daniel Lezcano <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions