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authorBiju Das <[email protected]>2021-06-26 09:13:37 +0100
committerGeert Uytterhoeven <[email protected]>2021-07-12 10:52:03 +0200
commitfd8c3f6c36eb093039d4aeb20cceee00c7c6ba1a (patch)
tree1ff9d0af260d9b8086c8106b4af4d6ceb38bf82c /tools/perf/scripts/python/export-to-postgresql.py
parente93c1373613fb2f3e59db5f13271f155820e6a67 (diff)
clk: renesas: r9a07g044: Fix P1 Clock
As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4. So fix the clock definitions for P1. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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