aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/export-to-postgresql.py
diff options
context:
space:
mode:
authorPaul Burton <[email protected]>2016-02-03 03:35:49 +0000
committerRalf Baechle <[email protected]>2016-03-29 14:18:18 +0200
commitfa8ff601d72bad3078ddf5ef17a5547700d06908 (patch)
tree74653d535d164057871ab6a72bbfc44df842cde3 /tools/perf/scripts/python/export-to-postgresql.py
parent19fb5818ed60ac2e9609ad16bc48116f4ce269a8 (diff)
MIPS: Fix MSA ld unaligned failure cases
Copying the content of an MSA vector from user memory may involve TLB faults & mapping in pages. This will fail when preemption is disabled due to an inability to acquire mmap_sem from do_page_fault, which meant such vector loads to unmapped pages would always fail to be emulated. Fix this by disabling preemption later only around the updating of vector register state. This change does however introduce a race between performing the load into thread context & the thread being preempted, saving its current live context & clobbering the loaded value. This should be a rare occureence, so optimise for the fast path by simply repeating the load if we are preempted. Additionally if the copy failed then the failure path was taken with preemption left disabled, leading to the kernel typically encountering further issues around sleeping whilst atomic. The change to where preemption is disabled avoids this issue. Fixes: e4aa1f153add "MIPS: MSA unaligned memory access support" Reported-by: James Hogan <[email protected]> Signed-off-by: Paul Burton <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: Leonid Yegoshin <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: James Cowgill <[email protected]> Cc: Markos Chandras <[email protected]> Cc: stable <[email protected]> # v4.3 Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/12345/ Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions