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authorClaudiu Beznea <[email protected]>2024-04-22 13:53:52 +0300
committerGeert Uytterhoeven <[email protected]>2024-04-25 20:12:14 +0200
commitf33dca9ed6f41c8acf2c17c402738deddb7d7c28 (patch)
tree4f4b4775731c2c34e99e075f9333336264f15344 /tools/perf/scripts/python/export-to-postgresql.py
parent2d03ce9cd7bdd1e29772f8ecf7769535361c7eaa (diff)
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S
The driver will be modified (in the next commits) to be able to specify individual power domain IDs for each IP. The driver will still support #power-domain-cells = <0>, thus, previous users are not affected. The #power-domain-cells = <1> has been instantiated only for RZ/G3S at the moment, as individual platform clock drivers need to be adapted for this to be supported on the rest of the SoCs. Also, the description for #power-domain-cells is updated with links to per-SoC power domain IDs. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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