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authorPeng Fan <[email protected]>2020-11-01 19:23:54 +0800
committerStephen Boyd <[email protected]>2020-11-04 17:13:12 -0800
commitc277ca155d2f0028a5c79708426d3f79b54a5fc1 (patch)
tree21bbb33da3f32f2f920492e9bb85f4bdb4e7b6f0 /tools/perf/scripts/python/export-to-postgresql.py
parent8d8c3131248d7e9c6c8ab448e1c6cb6bd7755e9c (diff)
clk: imx8m: fix bus critical clk registration
noc/axi/ahb are bus clk, not peripheral clk. Since peripheral clk has a limitation that for peripheral clock slice, IP clock slices must be stopped to change the clock source. However if the bus clk is marked as critical clk peripheral, the assigned clock parent operation will fail. So we added CLK_SET_PARENT_GATE flag to avoid glitch. And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") Reviewed-by: Abel Vesa <[email protected]> Reported-by: Abel Vesa <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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