diff options
| author | Martin Blumenstingl <[email protected]> | 2018-04-22 12:53:30 +0200 |
|---|---|---|
| committer | Linus Walleij <[email protected]> | 2018-05-02 14:36:08 +0200 |
| commit | bf6f146f3221596d7e44dd3547b9d22782e31504 (patch) | |
| tree | 54f94dc6eca7455a7aa21d06228528d2dcc71763 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | b0d46cb598bed0b03921090ba5fb84ceb4c6f707 (diff) | |
pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals
These are only available on the Meson8m2 SoC (which uses the same
DesignWare Ethernet MAC as Meson8b).
The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII
PHYs or the RGMII TX clock (as far as we know the frequency is
controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP
block).
Signed-off-by: Martin Blumenstingl <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions