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author | Inochi Amaoto <[email protected]> | 2024-03-09 17:02:55 +0800 |
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committer | Inochi Amaoto <[email protected]> | 2024-04-11 15:28:56 +0800 |
commit | bb7b3419627eb34f3466022d1f4b3c942c09712d (patch) | |
tree | 61fb1541734e01c04eda11fb8d3472e843bdf4d8 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | 89a7056ed4f771e689729f7992ef5351e64e26c6 (diff) |
riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC
Add clock generator node for CV1800B and CV1812H.
Until now, It uses DT override to minimize duplication. This may
change in the future. See the last link for the discussion on
maintaining DT of CV1800 series.
Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Chen Wang <[email protected]>
Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <[email protected]>
Signed-off-by: Chen Wang <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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