PCI: mvebu: Avoid changing the SCC bit in the Link Status register

It seems on later Armada 38x, the slot clock configuration bit is not
read-only, but can be written.  This means that our RW1C protection ends up
clearing this bit when the link control register is written.

Adjust the mask so that we only avoid writing '1' bits to the RW1C bits of
this register (bits 15 and 14 of the link status) rather than masking out
all the status register bits.

Signed-off-by: Russell King <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>

0 files changed, 0 insertions, 0 deletions