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authorXu Yang <[email protected]>2023-11-20 17:33:13 +0800
committerWill Deacon <[email protected]>2023-12-05 14:12:07 +0000
commitafd83967e7bb9b41ee71153b868dcf94e43c2d7a (patch)
treea219e60831b45c10b444db7897bc50461ef13319 /tools/perf/scripts/python/export-to-postgresql.py
parent118eb89b1e7f6807776c012cffc5c9b07fd26164 (diff)
perf: fsl_imx8_ddr: Add AXI ID PORT CHANNEL filter support
This is the extension of AXI ID filter. Filter is defined with 2 configuration registers per counter 1-3 (counter 0 is not used for filtering and lacks these registers). * Counter N MASK COMP register - AXI_ID and AXI_MASKING. * Counter N MUX CNTL register - AXI CHANNEL and AXI PORT. -- 0: address channel -- 1: data channel This filter is exposed to userspace as an additional (channel, port) pair. The definition of axi_channel is inverted in userspace, and it will be reverted in driver automatically. AXI filter of Perf Monitor in DDR Subsystem, only a single port0 exist, so axi_port is reserved which should be 0. e.g. perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd Signed-off-by: Xu Yang <[email protected]> Reviewed-by: Frank Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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