diff options
| author | Peter Ujfalusi <[email protected]> | 2016-12-23 11:21:10 +0200 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2016-12-31 18:43:11 +0000 |
| commit | 63c3194b82530bd71fd49db84eb7ab656b8d404a (patch) | |
| tree | c21e4e4467dc29598477b248a2aecdb5374174e0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | a5de5b74a50113564a1e0850e2da96c37c35e55d (diff) | |
ASoC: tlv320aic3x: Mark the RESET register as volatile
The RESET register only have one self clearing bit and it should not be
cached. If it is cached, when we sync the registers back to the chip we
will initiate a software reset as well, which is not desirable.
Signed-off-by: Peter Ujfalusi <[email protected]>
Reviewed-by: Jarkko Nikula <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions