diff options
| author | Andrea Merello <[email protected]> | 2018-11-20 16:31:46 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2019-01-07 09:53:11 +0530 |
| commit | 5c094d4cac5ba78139f4d7169145b57af7f07981 (patch) | |
| tree | da727149d396b2122fd2fc75ad597c0614d15167 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 616f0f81d857e248a72b5af45ab185196556ae2e (diff) | |
dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors
Whenever a single or cyclic transaction is prepared, the driver
could eventually split it over several SG descriptors in order
to deal with the HW maximum transfer length.
This could end up in DMA operations starting from a misaligned
address. This seems fatal for the HW if DRE (Data Realignment Engine)
is not enabled.
This patch eventually adjusts the transfer size in order to make sure
all operations start from an aligned address.
Cc: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Andrea Merello <[email protected]>
Reviewed-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions