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authorJon Lin <[email protected]>2021-06-21 18:47:57 +0800
committerMark Brown <[email protected]>2021-06-23 12:35:41 +0100
commit4a47fcdb5f8b220a396e896a4efed51c13e27d8b (patch)
tree1ff7c9f09dfa4ab09d9f4e165104328b44e327cb /tools/perf/scripts/python/export-to-postgresql.py
parent0f4f58b847b23d79185ad20ecf629c9f913f4f41 (diff)
spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
The error here is to calculate the width as 8 bits. In fact, 16 bits should be considered. Signed-off-by: Jon Lin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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