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| author | Caesar Wang <[email protected]> | 2015-11-06 19:38:14 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2015-11-16 10:10:24 +0000 |
| commit | 2458c37779ddb91b4109949d86f5a5e193ba415b (patch) | |
| tree | 8175fc61436a56646e3b1d4f52f77931e550043e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 8005c49d9aea74d382f474ce11afbbc7d7130bec (diff) | |
ASoC: rockchip: i2s: change bclk and lrck according to sample rates
This patch sets the dividers autonomously.
when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.
As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.
Signed-off-by: Caesar Wang <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions