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| author | Catalin Popescu <[email protected]> | 2024-04-15 16:03:48 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2024-04-19 19:09:41 -0700 |
| commit | 1758c68c81b8b881818fcebaaeb91055362a82f8 (patch) | |
| tree | ab07e1278aba492dc694eb8b1ba7e5f8fafa08e6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | a09b2d6a3be5e7856e1a664bcfaaa3dcd6583b91 (diff) | |
clk: rs9: fix wrong default value for clock amplitude
According to 9FGV0241, 9FGV0441 & 9FGV0841 datasheets, the default
value for the clock amplitude is 0.8V, while the driver assumes 0.7V.
Additionally, define constants for default values for both clock
amplitude and spread spectrum and use them.
Fixes: 892e0ddea1aa ("clk: rs9: Add Renesas 9-series PCIe clock generator driver")
Signed-off-by: Catalin Popescu <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions