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authorKuninori Morimoto <[email protected]>2016-02-18 08:17:18 +0000
committerMark Brown <[email protected]>2016-02-20 00:53:02 +0900
commit0dc6bf75023a42895962800020583c19e0b87159 (patch)
tree5983ebb1ef8175631acf866851038257876e6744 /tools/perf/scripts/python/export-to-postgresql.py
parentc8e969a85ecb982dccf2ba13ba9aff9f1a68eab2 (diff)
ASoC: rsnd: tidyup SSI init/start sequence
SSI want to have SSIWSR settings and SSICR settings without EN bit when init, and SSICR EN bit only when start timing. Otherwise, SSI output signal might be unstable. Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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