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| author | Gareth Williams <[email protected]> | 2019-09-18 09:04:34 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2019-10-01 12:32:44 +0100 |
| commit | 47cf13bc763c891c6192184c5e5aa8c1b331b2ff (patch) | |
| tree | 5d7d177898742098f398b0ef3a3940513c54c50b /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | da182a61fce01dbd7c4a78c68a34af110f00e36f (diff) | |
dt-bindings: snps,dw-apb-ssi: Add optional clock domain information
Note in the bindings documentation that pclk should be renamed if a clock
domain is used to enable the optional bus clock.
Signed-off-by: Gareth Williams <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions