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authorJonathan Cavitt <[email protected]>2023-11-02 10:58:31 -0700
committerAndi Shyti <[email protected]>2023-11-06 17:35:32 +0100
commit34df0a031d8f3488fe72627b041a1f82437fa6ec (patch)
treeb996db964689cf4b65a4718e30d921fba6721944 /tools/perf/scripts/python/compaction-times.py
parent27b086382c22efb7e0a16442f7bdc2e120108ef3 (diff)
drm/i915/gt: Temporarily disable CPU caching into DMA for MTL
FIXME: It is suspected that some Address Translation Service (ATS) issue on IOMMU is causing CAT errors to occur on some MTL workloads. Applying a write barrier to the ppgtt set entry functions appeared to have no effect, so we must temporarily use I915_MAP_WC in the map_pt_dma class of functions on MTL until a proper ATS solution is found. Signed-off-by: Jonathan Cavitt <[email protected]> CC: Chris Wilson <[email protected]> Reviewed-by: Radhakrishna Sripada <[email protected]> Acked-by: Andi Shyti <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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