diff options
| author | Chen-Yu Tsai <[email protected]> | 2017-10-10 11:20:02 +0800 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2017-10-11 09:53:13 +0200 |
| commit | cc67ae90be461ff78ed0b92681213e988138312a (patch) | |
| tree | cfbb6571408c1b4b02e9ffbd48c00d6467c21022 /tools/perf/scripts/python/call-graph-from-sql.py | |
| parent | 4b1c924b1fc15e68251ad0186b5004858d0f147b (diff) | |
drm/sun4i: hdmi: Allow using second PLL as TMDS clk parent
On SoCs with two display pipelines, it is possible that the two
pipelines are active at the same time, with potentially incompatible
dot clocks.
Let the HDMI encoder's TMDS clock go through all of its parents when
calculating possible clock rates. This allows usage of the second video
PLL as its parent.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-sql.py')
0 files changed, 0 insertions, 0 deletions