clk: aspeed: Support HPLL strapping on ast2400

The HPLL can be configured through a register (SCU24), however some
platforms chose to configure it through the strapping settings and do
not use the register. This was not noticed as the logic for bit 18 in
SCU24 was confused: set means programmed, but the driver read it as set
means strapped.

This gives us the correct HPLL value on Palmetto systems, from which
most of the peripheral clocks are generated.

Fixes: 5eda5d79e4be ("clk: Add clock driver for ASPEED BMC SoCs")
Cc: [email protected] # v4.15
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions