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| author | Jérémy Lefaure <[email protected]> | 2017-06-28 20:57:29 -0400 |
|---|---|---|
| committer | Borislav Petkov <[email protected]> | 2017-06-29 10:33:13 +0200 |
| commit | a8c8261425649da58bdf08221570e5335ad33a31 (patch) | |
| tree | 5be98bafe7520552305be37670e7c7ae909bc74e /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | 77641dacead2cbfe22d10f4e7c07867d86900057 (diff) | |
EDAC, i5000, i5400: Fix definition of NRECMEMB register
In the i5000 and i5400 drivers, the NRECMEMB register is defined as a
16-bit value, which results in wrong shifts in the code, as reported by
sparse.
In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21),
this register is a 32-bit register. A u32 value for the register fixes
the wrong shifts warnings and matches the datasheet.
Also fix the mask to access to the CAS bits [27:16] in the i5000 driver.
[1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf
[2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf
Signed-off-by: Jérémy Lefaure <[email protected]>
Cc: linux-edac <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Borislav Petkov <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions