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| author | Stefan Agner <[email protected]> | 2016-09-02 11:23:37 -0700 |
|---|---|---|
| committer | Stefan Agner <[email protected]> | 2016-09-05 12:11:50 -0700 |
| commit | 6cc4758ae91c0582f07e3c94c7de1ad0975feff5 (patch) | |
| tree | 8de56d6849f1b971e908a4eefdd9276b835318ed /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | 2b2fd56d7e92f134ecaae5c89e20f64dd0f95aa2 (diff) | |
drm/fsl-dcu: fix endian issue when using clk_register_divider
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.
Cc: [email protected]
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
Tested-by: Meng Yi <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions