diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:42 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:15 -0700 |
| commit | ea0e0178e101c8d4662a0db7424df057b88e2712 (patch) | |
| tree | cf13785f09c5155169c9f04f77b65aca7bedf84a /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
| parent | 95113bb705157f3518cec4ff0225a922507a0f8b (diff) | |
perf: RISC-V: Eliminate redundant interrupt enable/disable operations
The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). It can be done only once.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-7-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions