phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk

In preparation for support for additional platforms, convert the phy
register access clock to using the clk_bulk interfaces.

Newer SoCs like Google Tensor gs101 require additional clocks for
access to additional (different) register areas (PHY, PMA, PCS), and
converting to clk_bulk simplifies addition of those extra clocks.

Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Tested-by: Peter Griffin <[email protected]>
Tested-by: Will McVicker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>

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