diff options
| author | Claudiu Beznea <[email protected]> | 2024-06-14 10:19:21 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-06-27 18:16:39 +0200 |
| commit | c8bd9bd6446fa034a1877b553bf118606b37c025 (patch) | |
| tree | ce9ac9b2648249116ca7e1ca8996fe6e5ef4dbe3 /scripts/gdb/linux/lists.py | |
| parent | d6c5fc9add9eb7a0d5bd179ab07cbf43e32b28d8 (diff) | |
clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
that generates the RTC clock. Add clock, reset and power domain support
for it.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions