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authorKefeng Wang <[email protected]>2024-09-23 21:13:51 +0800
committerCatalin Marinas <[email protected]>2024-10-16 12:01:53 +0100
commita923705c69f7f4ebe6a5488c1f556bed12d28031 (patch)
treec51eb05da42a4a0caceabf0c250a18f2e6c7e68f /drivers/perf/arm-ccn.c
parent7ffc13e233951f15728c9d09db3cc8d9f6cf81f2 (diff)
arm64: optimize flush tlb kernel range
Currently the kernel TLBs is flushed page by page if the target VA range is less than MAX_DVM_OPS * PAGE_SIZE, otherwise we'll brutally issue a TLBI ALL. But we could optimize it when CPU supports TLB range operations, convert to use __flush_tlb_range_op() like other tlb range flush to improve performance. Co-developed-by: Yicong Yang <[email protected]> Signed-off-by: Yicong Yang <[email protected]> Signed-off-by: Kefeng Wang <[email protected]> Reviewed-by: Anshuman Khandual <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'drivers/perf/arm-ccn.c')
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