diff options
| author | Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> | 2023-09-28 22:15:39 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:42:08 -0500 |
| commit | 328e089bfb376a9817a260542fbea0fe9e0975ac (patch) | |
| tree | a396860a1803f01dd1462ad48bef1d9ee8adde0c /drivers/gpu/drm/xe/xe_vm.c | |
| parent | 30603b5b0f8678fff799f4e3e2b45b8c08648575 (diff) | |
drm/xe: Leverage ComputeCS read L3 caching
On platforms that support read L3 caching, set the default mocs index in
CCS RING_CMD_CTL to leverage the read caching in L3.
Currently PVC and Xe2 platforms have the support.
Bspec: 72161
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230929051539.3157441-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_vm.c')
0 files changed, 0 insertions, 0 deletions