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authorThomas Zimmermann <[email protected]>2023-01-31 14:18:33 +0100
committerThomas Zimmermann <[email protected]>2023-01-31 14:18:33 +0100
commitdf5bf3b942a8d344bd9cbbe6ac31c9a2ea1557a4 (patch)
treebfbcbe56b9f4f8b1e44242b80800a68b2ae5b2d6 /drivers/gpu/drm/i915/display/intel_dpll.c
parent532a38292c7213aa6d950e6a1b86659d08b5aa67 (diff)
parentaebd8f0c6f8280ba35bc989f4a9ea47469d3589a (diff)
Merge drm/drm-next into drm-misc-next
Backmerging to get v6.2-rc6. Signed-off-by: Thomas Zimmermann <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_dpll.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c236aafe9be0..4e9c18be7e1f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1910,7 +1910,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, DPLL_MD(PIPE_B),
crtc_state->dpll_hw_state.dpll_md);
intel_de_write(dev_priv, CBR4_VLV, 0);
- dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
+ dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
/*
* DPLLB VGA mode also seems to cause problems.