diff options
| author | Jun Lei <Jun.Lei@amd.com> | 2019-05-27 14:15:27 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:14 -0500 |
| commit | 6e17b5b8a846850d73e06dc778e7d5c3ef0423f9 (patch) | |
| tree | 49634762b7d6c7296eab3fd363f381a0ac3eb01b /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | cf020d49b3c4ef6ab6f26be3dbf2f36b3df9f797 (diff) | |
drm/amd/display: update DCN2 uclk switch time
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated
[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index e3c1debf2597..6f01830fc020 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -195,12 +195,10 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); } - if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) { - clk_mgr_base->clks.p_state_change_support = false; - pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, false); - } else if (safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) { + if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; - pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); + if (pp_smu && pp_smu->set_pstate_handshake_support) + pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); } if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { |