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| author | Suravee Suthikulpanit <[email protected]> | 2019-11-20 07:55:48 -0600 |
|---|---|---|
| committer | Joerg Roedel <[email protected]> | 2019-12-23 14:06:15 +0100 |
| commit | 813071438e83d338ba5cfe98b3b26c890dc0a6c0 (patch) | |
| tree | a5b3e71f7e71480ed2793d202e5ca54ebb166d00 /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | |
| parent | 387caf0b759ac437a65ad5d59665558025f350fc (diff) | |
iommu/amd: Check feature support bit before accessing MSI capability registers
The IOMMU MMIO access to MSI capability registers is available only if
the EFR[MsiCapMmioSup] is set. Current implementation assumes this bit
is set if the EFR[XtSup] is set, which might not be the case.
Fix by checking the EFR[MsiCapMmioSup] before accessing the MSI address
low/high and MSI data registers via the MMIO.
Fixes: 66929812955b ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Joerg Roedel <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c')
0 files changed, 0 insertions, 0 deletions