diff options
| author | Marek Vasut <[email protected]> | 2024-01-18 23:02:31 +0100 |
|---|---|---|
| committer | Robert Foss <[email protected]> | 2024-01-23 12:18:01 +0100 |
| commit | f86ae204bec4e72f14f7d4fd586d7ef9729614dc (patch) | |
| tree | 46d8e723cd8c7fb636078484426bf39e06da870b /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | |
| parent | 71fc3249f50ac22f495185872e71393cfa9d6f07 (diff) | |
drm/bridge: tc358767: Limit the Pixel PLL input range
According to new configuration spreadsheet from Toshiba for TC9595,
the Pixel PLL input clock have to be in range 6..40 MHz. The sheet
calculates those PLL input clock as reference clock divided by both
pre-dividers. Add the extra limit.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Signed-off-by: Robert Foss <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
0 files changed, 0 insertions, 0 deletions