diff options
| author | Mark Brown <[email protected]> | 2021-10-07 22:35:49 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-10-07 22:35:49 +0100 |
| commit | a0ecee320158909135dd182d2eefbf18c114e8d2 (patch) | |
| tree | 78c4b8af6d370f7402746930c123f9f97c5c66d2 /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | 5fe7bd5a37ff0d77936f8e38313db5da2dd53f70 (diff) | |
| parent | da21fde0fdb393c2fbe0ae0735cc826cd55fd46f (diff) | |
Merge series "spi: Various Cleanups" from Uwe Kleine-König <[email protected]>:
Hello,
while trying to understand how the spi framework makes use of the core
device driver stuff (to fix a deadlock) I found these simplifications
and improvements.
They are build-tested with allmodconfig on arm64, m68k, powerpc, riscv,
s390, sparc64 and x86_64.
Best regards
Uwe
Uwe Kleine-König (4):
spi: Move comment about chipselect check to the right place
spi: Remove unused function spi_busnum_to_master()
spi: Reorder functions to simplify the next commit
spi: Make several public functions private to spi.c
Documentation/spi/spi-summary.rst | 8 -
drivers/spi/spi.c | 237 ++++++++++++------------------
include/linux/spi/spi.h | 55 -------
3 files changed, 95 insertions(+), 205 deletions(-)
base-commit: 9e1ff307c779ce1f0f810c7ecce3d95bbae40896
--
2.30.2
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 7a7316731911..dc50c05f23fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -837,6 +837,28 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) return 0; } +/* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ +static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) +{ + u64 micro_tile_mode; + + /* Zero swizzle mode means linear */ + if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) + return 0; + + micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); + switch (micro_tile_mode) { + case 0: /* DISPLAY */ + case 3: /* RENDER */ + return 0; + default: + drm_dbg_kms(afb->base.dev, + "Micro tile mode %llu not supported for scanout\n", + micro_tile_mode); + return -EINVAL; + } +} + static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, unsigned int *width, unsigned int *height) { @@ -1103,6 +1125,7 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { + struct amdgpu_device *adev = drm_to_adev(dev); int ret, i; /* @@ -1122,6 +1145,14 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, if (ret) return ret; + if (!dev->mode_config.allow_fb_modifiers) { + drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, + "GFX9+ requires FB check based on format modifier\n"); + ret = check_tiling_flags_gfx6(rfb); + if (ret) + return ret; + } + if (dev->mode_config.allow_fb_modifiers && !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { ret = convert_tiling_flags_to_modifier(rfb); |