diff options
| author | Heiko Stuebner <[email protected]> | 2022-07-07 01:15:36 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2022-08-03 17:29:59 -0700 |
| commit | d20ec7529236a2fcdb2d856fc0bd80b409a217fc (patch) | |
| tree | 97c41e3c370f0ec170fb1b3aab81c42e8f1d105e /arch/riscv/mm/dma-noncoherent.c | |
| parent | 1631ba1259d6d7f49b6028f2a1a0fa02be1c522a (diff) | |
riscv: implement cache-management errata for T-Head SoCs
The T-Head C906 and C910 implement a scheme for handling
cache operations different from the generic Zicbom extension.
Add an errata for it next to the generic dma coherency ops.
Reviewed-by: Samuel Holland <[email protected]>
Tested-by: Samuel Holland <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'arch/riscv/mm/dma-noncoherent.c')
0 files changed, 0 insertions, 0 deletions