diff options
| author | Anup Patel <[email protected]> | 2023-03-28 09:22:17 +0530 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2023-04-08 11:26:23 +0100 |
| commit | 3ee92565b83ecc08e5b0c878dd87a2973eaca2ea (patch) | |
| tree | e1ed67069e6835bec9825cc9e5d9425770e71f07 /arch/riscv/kernel/irq.c | |
| parent | 197b6b60ae7bc51dd0814953c562833143b292aa (diff) | |
RISC-V: Clear SIP bit only when using SBI IPI operations
The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but read-only for M-mode so we clear this bit only when using
SBI IPI operations.
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'arch/riscv/kernel/irq.c')
0 files changed, 0 insertions, 0 deletions