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authorSergio Paracuellos <[email protected]>2023-06-19 06:09:39 +0200
committerThomas Bogendoerfer <[email protected]>2023-06-21 14:50:23 +0200
commit201ddc05777cd8e084b508bcdda22214bfe2895e (patch)
tree4a0799b994e622902699b0f5a05e530cbe66861b /arch/mips/ralink/clk.c
parent04b153abdfcbaba70ceef5a846067d4447fd0078 (diff)
mips: ralink: remove reset related code
A proper clock driver for ralink SoCs has been added. This driver is also a reset provider for the SoC. Hence there is no need to have reset related code in 'arch/mips/ralink' folder anymore. The only code that remains is the one related with mips_reboot_setup where a PCI reset is performed. We maintain this because I cannot test old ralink board with PCI to be sure all works if we remove also this code. Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
Diffstat (limited to 'arch/mips/ralink/clk.c')
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