diff options
| author | Bjorn Helgaas <[email protected]> | 2024-01-03 17:16:03 -0600 |
|---|---|---|
| committer | Thomas Bogendoerfer <[email protected]> | 2024-01-08 10:39:12 +0100 |
| commit | 2f9060b1db4aa2c21c248e34476d8936a2b69cf6 (patch) | |
| tree | 666738efd029662d2e38b60c3fe3fd398c38376d /arch/mips/mm/c-r4k.c | |
| parent | 8e1803900ef1b61ed33e6963d9e6a95028b41110 (diff) | |
MIPS: Fix typos
Fix typos, most reported by "codespell arch/mips". Only touches comments,
no code changes.
Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: [email protected]
Reviewed-by: Randy Dunlap <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>
Diffstat (limited to 'arch/mips/mm/c-r4k.c')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 187d1c16361c..20d37773b162 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1654,7 +1654,7 @@ static void coherency_setup(void) /* * c0_status.cu=0 specifies that updates by the sc instruction use - * the coherency mode specified by the TLB; 1 means cachable + * the coherency mode specified by the TLB; 1 means cacheable * coherent update on write will be used. Not all processors have * this bit and; some wire it to zero, others like Toshiba had the * silly idea of putting something else there ... |