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authorMatthew Wilcox (Oracle) <[email protected]>2023-08-02 16:13:41 +0100
committerAndrew Morton <[email protected]>2023-08-24 16:20:21 -0700
commit876397837d582ce72f977ac3e635ce74eebcecc9 (patch)
tree8ff3ffd26f7f0396484873e81cdc95374c49a44f /arch/mips/include/asm/pgtable-bits.h
parent9ff633944165d11c53c088d9596db3da66e90396 (diff)
ia64: implement the new page table range API
Add PFN_PTE_SHIFT, update_mmu_cache_range() and flush_dcache_folio(). Change the PG_arch_1 (aka PG_dcache_clean) flag from being per-page to per-folio, which makes arch_dma_mark_clean() and mark_clean() a little more exciting. [[email protected]: fix folio_size() handling] Link: https://lkml.kernel.org/r/[email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Matthew Wilcox (Oracle) <[email protected]> Acked-by: Mike Rapoport (IBM) <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
Diffstat (limited to 'arch/mips/include/asm/pgtable-bits.h')
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