diff options
| author | Ingo Molnar <[email protected]> | 2016-06-08 09:26:46 +0200 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2016-06-08 09:26:46 +0200 |
| commit | 616d1c1b98ac79f30216a57a170dd7cea19b3df3 (patch) | |
| tree | 6f244c2e5a7160190e73bc82b4cd7fa7bb22ee31 /arch/mips/include/asm/hazards.h | |
| parent | a4f144ebbdf6f7807c477bce8e136047ed27321f (diff) | |
| parent | c8ae067f2635be0f8c7e5db1bb74b757d623e05b (diff) | |
Merge branch 'linus' into perf/core, to refresh the branch
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'arch/mips/include/asm/hazards.h')
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 7b99efd31074..e0fecf206f2c 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -22,7 +22,8 @@ /* * TLB hazards */ -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) && !defined(CONFIG_CPU_CAVIUM_OCTEON) +#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \ + !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT) /* * MIPSR2 defines ehb for hazard avoidance @@ -57,8 +58,8 @@ * address of a label as argument to inline assembler. Gas otoh has the * annoying difference between la and dla which are only usable for 32-bit * rsp. 64-bit code, so can't be used without conditional compilation. - * The alterantive is switching the assembler to 64-bit code which happens - * to work right even for 32-bit code ... + * The alternative is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code... */ #define instruction_hazard() \ do { \ @@ -132,8 +133,8 @@ do { \ * address of a label as argument to inline assembler. Gas otoh has the * annoying difference between la and dla which are only usable for 32-bit * rsp. 64-bit code, so can't be used without conditional compilation. - * The alterantive is switching the assembler to 64-bit code which happens - * to work right even for 32-bit code ... + * The alternative is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code... */ #define __instruction_hazard() \ do { \ @@ -155,8 +156,8 @@ do { \ } while (0) #elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \ + defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |