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authorIngo Molnar <[email protected]>2016-06-08 09:26:46 +0200
committerIngo Molnar <[email protected]>2016-06-08 09:26:46 +0200
commit616d1c1b98ac79f30216a57a170dd7cea19b3df3 (patch)
tree6f244c2e5a7160190e73bc82b4cd7fa7bb22ee31 /arch/mips/include/asm/cacheops.h
parenta4f144ebbdf6f7807c477bce8e136047ed27321f (diff)
parentc8ae067f2635be0f8c7e5db1bb74b757d623e05b (diff)
Merge branch 'linus' into perf/core, to refresh the branch
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
-rw-r--r--arch/mips/include/asm/cacheops.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index c3212ff26723..8031fbc6b69a 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -21,6 +21,7 @@
#define Cache_I 0x00
#define Cache_D 0x01
#define Cache_T 0x02
+#define Cache_V 0x02 /* Loongson-3 */
#define Cache_S 0x03
#define Index_Writeback_Inv 0x00
@@ -107,4 +108,9 @@
*/
#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
+/*
+ * Loongson3-specific cacheops
+ */
+#define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv)
+
#endif /* __ASM_CACHEOPS_H */