diff options
| author | Guo Ren <[email protected]> | 2020-12-24 05:59:57 +0000 |
|---|---|---|
| committer | Guo Ren <[email protected]> | 2021-01-12 09:52:41 +0800 |
| commit | 3b756ccddb8a75563900cd603c83160b43f3d691 (patch) | |
| tree | af6428140af2760616d577a0b1e515a45b58207c /arch/csky/mm/init.c | |
| parent | c109f42450ec25283169dd6c0acce8d053493732 (diff) | |
csky: Fix TLB maintenance synchronization problem
TLB invalidate didn't contain a barrier operation in csky cpu and
we need to prevent previous PTW response after TLB invalidation
instruction. Of cause, the ASID changing also needs to take care
of the issue.
CPU0 CPU1
=============== ===============
set_pte
sync_is() -> See the previous set_pte for all harts
tlbi.vas -> Invalidate all harts TLB entry & flush pipeline
Signed-off-by: Guo Ren <[email protected]>
Diffstat (limited to 'arch/csky/mm/init.c')
| -rw-r--r-- | arch/csky/mm/init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/csky/mm/init.c b/arch/csky/mm/init.c index 8170d7ce116b..bc05a3be9d57 100644 --- a/arch/csky/mm/init.c +++ b/arch/csky/mm/init.c @@ -164,7 +164,7 @@ void __init mmu_init(unsigned long min_pfn, unsigned long max_pfn) /* Setup page mask to 4k */ write_mmu_pagemask(0); - setup_pgd(swapper_pg_dir); + setup_pgd(swapper_pg_dir, 0); } void __init fixrange_init(unsigned long start, unsigned long end, |