diff options
author | Arnd Bergmann <[email protected]> | 2021-01-18 12:45:46 +0100 |
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committer | Arnd Bergmann <[email protected]> | 2021-01-20 09:30:45 +0100 |
commit | a579fcfa8e49cc77ad59211bb18bc5004133e6a0 (patch) | |
tree | 51eee55987ddb1fdd125922606b71bafdf3b9bb8 /arch/c6x/include/asm/cacheflush.h | |
parent | bd97ad35e816daf9a72ee35d3524d8417f7cf414 (diff) |
c6x: remove architecture
The c6x architecture was added to the kernel in 2011 at a time when
running Linux on DSPs was widely seen as the logical evolution.
It appears the trend has gone back to running Linux on Arm based SoCs
with DSP, using a better supported software ecosystem, and having better
real-time behavior for the DSP code. An example of this is TI's own
Keystone2 platform.
The upstream kernel port appears to no longer have any users. Mark
Salter remained avaialable to review patches, but mentioned that
he no longer has access to working hardware himself. Without any
users, it's best to just remove the code completely to reduce the
work for cross-architecture code changes.
Many thanks to Mark for maintaining the code for the past ten years.
Link: https://lore.kernel.org/lkml/[email protected]/
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'arch/c6x/include/asm/cacheflush.h')
-rw-r--r-- | arch/c6x/include/asm/cacheflush.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/c6x/include/asm/cacheflush.h b/arch/c6x/include/asm/cacheflush.h deleted file mode 100644 index 10922d528de6..000000000000 --- a/arch/c6x/include/asm/cacheflush.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Port on Texas Instruments TMS320C6x architecture - * - * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated - * Author: Aurelien Jacquiot ([email protected]) - */ -#ifndef _ASM_C6X_CACHEFLUSH_H -#define _ASM_C6X_CACHEFLUSH_H - -#include <linux/spinlock.h> - -#include <asm/setup.h> -#include <asm/cache.h> -#include <asm/mman.h> -#include <asm/page.h> -#include <asm/string.h> - -/* - * physically-indexed cache management - */ -#define flush_icache_range(s, e) \ -do { \ - L1D_cache_block_writeback((s), (e)); \ - L1P_cache_block_invalidate((s), (e)); \ -} while (0) - -#define flush_icache_page(vma, page) \ -do { \ - if ((vma)->vm_flags & PROT_EXEC) \ - L1D_cache_block_writeback_invalidate(page_address(page), \ - (unsigned long) page_address(page) + PAGE_SIZE)); \ - L1P_cache_block_invalidate(page_address(page), \ - (unsigned long) page_address(page) + PAGE_SIZE)); \ -} while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { \ - memcpy(dst, src, len); \ - flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ -} while (0) - -#include <asm-generic/cacheflush.h> - -#endif /* _ASM_C6X_CACHEFLUSH_H */ |