diff options
author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:26 +0000 |
---|---|---|
committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:15 +0000 |
commit | f4e9ce12dd88d33c25019e2053ade587d7b95969 (patch) | |
tree | f3b8291b21f58494d4cb5509e453372f337b16dd /arch/arm64/include | |
parent | 849cc9bd9f0ef532c208d1cc01a824dc119646e3 (diff) |
arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
Convert ID_ISAR5_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-28-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r-- | arch/arm64/include/asm/sysreg.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 0a63c39407f2..04a6e44427a9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -173,7 +173,6 @@ #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) -#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) @@ -689,13 +688,6 @@ #define ID_DFR1_EL1_MTPMU_SHIFT 0 -#define ID_ISAR5_EL1_RDM_SHIFT 24 -#define ID_ISAR5_EL1_CRC32_SHIFT 16 -#define ID_ISAR5_EL1_SHA2_SHIFT 12 -#define ID_ISAR5_EL1_SHA1_SHIFT 8 -#define ID_ISAR5_EL1_AES_SHIFT 4 -#define ID_ISAR5_EL1_SEVL_SHIFT 0 - #define ID_ISAR6_EL1_I8MM_SHIFT 24 #define ID_ISAR6_EL1_BF16_SHIFT 20 #define ID_ISAR6_EL1_SPECRES_SHIFT 16 |