irqchip: gic: Perform the gic_secondary_init() call via CPU notifier

All the calls to gic_secondary_init() pass 0 as the first argument.
Since this function is called on each CPU when starting, it can be done
in a platform-independent way via a CPU notifier registered by the GIC
code.

Signed-off-by: Catalin Marinas <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Viresh Kumar <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Simon Horman <[email protected]>
Tested-by: Simon Horman <[email protected]>
Acked-by: Srinidhi Kasagar <[email protected]>
Tested-by: Dinh Nguyen <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Tested-by: Marc Zyngier <[email protected]>
Cc: Russell King <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: David Brown <[email protected]>
Cc: Bryan Huntsman <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Magnus Damm <[email protected]>
Cc: Shiraz Hashim <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Barry Song <[email protected]>

1 files changed, 0 insertions, 7 deletions

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a..e7a449758ab5 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -67,13 +67,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
 							4, 0, 0, 0, 0, 0);
 
 	/*
-	 * If any interrupts are already enabled for the primary
-	 * core (e.g. timer irq), then they will not have been enabled
-	 * for us: do so
-	 */
-	gic_secondary_init(0);
-
-	/*
 	 * Synchronise with the boot thread.
 	 */
 	spin_lock(&boot_lock);